It may attribute to thicker Tox, and more partial depleted. MG device with sharp corner shows better short channel behavior than the rounded corner NTUEE Seminar 9ģ4 Double-humps induced by cap transistorģ0x30nm structure, Tox=3nm, Lg=1mm, Nsub=5e18cm-3 Cap transistor induced lower Vt is very significant. Z corner y flat Vg=0.2 V 2D current density distribution z y Vg=1 V 2D current density distribution NTUEE Seminar 9ģ2 3D Simulation w/ Various Shape of Corner

Vg=0.2 V Vg=1 V z z S D G y y 2D current density distribution 2D current density distribution DESSIS 3-D device simulator Ideal rectangular fin shape Nsub=1e15cm-3 NTUEE Seminar 9ģ1 Corner Effect Nsub=5e18cm-3 corner flat Vg=0.2 V Vg=1 V 133, 2003 NTUEE Seminar 9ģ0 Corner Effect DESSIS 3-D device simulator Krivokapic et al., IEDM 2002) Potential issues include: - dopant penetration - thermal stability - stress/adhesion - gate dielectric reliability NTUEE Seminar 9ĭifferent Vth at corner region Significant subthreshold leakage current Strong corner radius, body doping dependence B. Choi et al., IEDM 2002 Vt shift Lg=80nm, TSi=10nm Vds=0.05V |Vt|=0.2V for lightly doped body, and is adjustable by N+ implantation Alternative technique: Full silicidication (NiSi) of n+/p+ Si gates (J. Need low VT’s for speed Inverter Response VDD VIN= VTN VIN= VDD-VTP Output VDD Input NTUEE Seminar 9Ģ6 Gate Work Function Single gate material VTn = -VTp = 0.4V N+/P+ Polyįor low body doping, desired FM values are: ~ 4.5 eV for NMOS ~ 5.0 eV for PMOS Need two separate work functions for NMOS and PMOS! NTUEE Seminar 9Ģ7 Molybdenum FM Engineering by Ion ImplantationĪnneal time = 15m except for 900oC (15s) TMo = 15nm FM can be lowered by N+ implantation and thermal anneal DFM increases with dose energy (N segregates to SiO2 interface & forms Mo2N) P. Super HOT: SOI version DSB: bulk version NTUEE Seminar 9Ģ5 VT: What CMOS Needs… Need symmetrical VT’s for proper CMOS operation Inverter Non-(100) orientation saves area Higher PMOS Idsat reduces drawn W 45º orientation is less area efficient for smaller W These devices are small anyway…does it matter? Use only in critical path? NTUEE Seminar 9

Gate Source Drain Gate Source Drain (110) PMOS (100) NMOS Trade off layout area for performance NTUEE Seminar 9Ģ3 FinFET Layout Area Non-(100) orientation saves area Net delay improvement Trade off h and e NOR: PMOS stack h very important Most improvement NAND: NMOS stack h less important Least improvement Lgate=35nm h, e NOR Inv NAND (100) (111) (110) (100) NMOS (110) PMOS NTUEE Seminar 9Ģ2 Optimized FinFET (110) PMOS (100) NMOS e is degraded, h is enhanced Can we benefit from changing the N/P ratio? NTUEE Seminar 9Ģ1 Gate Delay PMOS enhancement (20%) is larger than NMOS degradation (8%) (110) Surface Gate Source Drain (110) (100) ~(111) (110) Rotation by 45º changes orientation from (110) to (100) Intermediate rotation similar to (111) NTUEE Seminar 9Ģ0 How Mobility Changes By shifting away from (100): Kuroda Keio University NTUEE Seminar 9Ħ Issues for Scaling Lg to (110) Surface (110) (100) ~(111) (110) Leakage current is the primary barrier to scaling To suppress leakage, we need to employ: Higher body doping  lower carrier mobility, higher junction capacitance, increased junction leakage Thinner gate dielectric  higher gate leakage Ultra-shallow S/D junctions  higher Rseries G S D Desired characteristics: - High ON current (Idsat) - Low OFF current Substrate Gate Source Drain Leff Nsub Xj Lg Tox courtesy of Prof. Improved performance Greater circuit functionality Source: Intel NTUEE Seminar 9 MOSFET Scaling ITRS 2001 Projection The first transistor 1947 The Power5 microprocessor Technology Scaling Investment Market Growth Better Performance/Cost Same transistor design concept NTUEE Seminar 9Ĥ Scaling : Moore’s law Technology Drivers Reduced cost / function

1 Recent Development of FinFET Technology for CMOS Logic and MemoryĬhung-Hsun Lin EECS Department University of California at BerkeleyĢ Outline Why FinFET Recent FinFET Develop Memory ConclusionįinFET process Unique features of FinFET Mobility, workfunction engineering, corner effect, QM, volume inversion Issues Recent FinFET Develop Triple-gate FinFET, Omega FET, Nanowire FinFET, Independent gate, Multi-channel FinFET, Metal-gate/high-K FinFET, Strained FinFET, Bulk FinFET Memory DRAM, SONOS, SRAM Conclusion NTUEE Seminar 9

1nm transistor gate